Electronic device

ABSTRACT

An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims priority of Korean Patent Application No. 10-2017-0039233, entitled “ELECTRONIC DEVICE” and filed on Mar. 28, 2017, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic devices or appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, there is a demand for electronic devices capable of storing information in various electronic devices or appliances such as a computer, a portable communication device, and so on, and research and development for such electronic devices have been conducted. Examples of such electronic devices include electronic devices which can store data using a characteristic switched between different resistant states according to an applied voltage or current, and can be implemented in various configurations, for example, a resistive random access memory (RRAM), a phase change random access memory (PRAM), an ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM an E-fuse, etc.

SUMMARY

The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device and a method for fabricating the same, in which an electronic device includes a semiconductor memory which is capable of improving characteristics of a variable resistance element.

In one aspect, an electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.

Implementations of the above electronic device may include one or more the following.

The free layer may have a spacer exchange coupling constant equal to or less than 0.3. The second magnetic layer may be disposed adjacent to the tunnel barrier layer and have a greater thickness than the first magnetic layer. The second magnetic layer may include an ahoy including Co, Fe and B. The first magnetic layer may have a crystalline structure including a hexagonal dose packed (hcp) (0001) structure or a face centered cubic (fcc) (111) structure, or an amorphous structure. The first magnetic layer may include a stack structure including Co/Pt, Co/Pd, Co/Ir or Co/Ru, an alloy including Co, or a combination thereof. The spacer may include an amorphous material, a metal, a metal nitride, a metal oxide or a combination thereof, and a material and a thickness of the spacer may be selected so as to satisfy a condition of a spacer exchange coupling constant≤0.3. The semiconductor memory may further include an under layer disposed below the free layer and improving perpendicular magnetic anisotropy of the free layer. The under layer may include a nitride or a carbide having a wurzite structure. The under layer may include AIN.

The electronic device may further include a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessors.

The electronic device may further include a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

The electronic device may further include a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

The electronic device may further include a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

The electronic device may further include a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

In another aspect, an electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer, and wherein, at the time of magnetization reversal, the second magnetic layer may first undergo magnetization reversal and then the first magnetic layer may undergo magnetization reversal with the help of a stray field generated by the second magnetic layer.

Implementations of the above electronic device may include one or more the following.

The free layer may have a spacer exchange coupling constant equal to or less than 0.3. The second magnetic layer may be disposed adjacent to the tunnel barrier layer and have a greater thickness than the first magnetic layer. The second magnetic layer may include an alloy including Co, Fe and B. The first magnetic layer may have a crystalline structure including a hexagonal close packed (hcp (0001) structure or a face centered cubic (fcc) (111) structure, or an amorphous structure. The first magnetic layer may include a stack structure including Co/Pt, Co/Pd, Co/Ir or Co/Ru, an alloy including Co, or a combination thereof. The spacer may include an amorphous material, a metal, a metal nitride, a metal oxide or a combination thereof, and a material and a thickness of the spacer may be selected so as to satisfy a condition of a spacer exchange coupling constant≤0.3. The semiconductor memory may further include an under layer disposed below the free layer and improving perpendicular magnetic anisotropy of the free layer. The under layer may include a nitride or a carbide having a wurzite structure. The under layer may include AlN.

In further another aspect, an electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; memory cells formed over the substrate, each memory cell including a free layer having a variable magnetization direction; and switching elements formed over the substrate and coupled to the memory cells, respectively, to select or de-select the memory cells, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.

Implementations of the above electronic device may include one or more the following.

Each memory cell may include a magnetic tunnel junction structure that includes the free layer, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer. The free layer may have a spacer exchange coupling constant equal to or less than 0.3. The second magnetic layer may be disposed adjacent to the tunnel barrier layer and have a greater thickness than the first magnetic layer. The second magnetic layer may include an alloy including Co, Fe and B. The first magnetic layer may have a crystalline structure including a hexagonal close packed (hcp) (0001) structure or a face centered cubic (fcc) (111) structure, or an amorphous structure. The first magnetic layer may include a stack structure including Co/Pt, Co/Pd, Co/Ir or Co/Ru, an alloy including Co, or a combination thereof. The spacer may include an amorphous material, a metal, a metal nitride, a metal oxide or a combination thereof, and a material and a thickness of the spacer may be selected so as to satisfy a condition of a spacer exchange coupling constant≤0.3. At the time of magnetization reversal, the second magnetic layer may first undergo magnetization reversal and then the first magnetic layer may undergo magnetization reversal with the help of a stray field generated by the second magnetic layer. The semiconductor memory may further include an under layer disposed below the free layer and improving perpendicular magnetic anisotropy of the free layer. The under layer may include a nitride or a carbide having a urzite structure. The under layer may include AlN.

These and other aspects, implementations and associated advantages are described in greater detail in the drawings, the description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a variable resistance element in accordance with a comparative example.

FIG. 2 is a cross-sectional view illustrating a variable resistance element in accordance with an implementation of the present disclosure.

FIG. 3 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with an implementation of the present disclosure.

FIG. 4 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with another implementation of the present disclosure.

FIG. 5 is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

FIG. 6 is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

FIG. 7 is an example of configuration of a system implementing memory circuitry based on the disclosed technology.

FIG. 8 is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

FIG. 9 is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

The drawings may not be necessarily to scale and in some instances, proportions of at least some of substrates in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or implementations. In presenting a specific example in a drawing or description having two or more layers in a multi-layer substrate, the relative positioning relationship of such layers or the sequence of arranging the layers as shown reflects a particular implementation for the described or illustrated example and a different relative positioning relationship or sequence of arranging the layers may be possible. In addition, a described or illustrated example of a multi-layer substrate may not reflect all layers present in that particular multilayer substrate (e.g., one or more additional layers can be present between two illustrated layers). As a specific example, when a first layer in a described or illustrated multi-layer substrate is referred to as being “on” or “over” a second layer or “on” or “over” a substrate, the first layer may be directly formed on the second layer or the substrate but may also represent a substrate where one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

Prior to explaining implementations of the present disclosure, a variable resistance element in accordance with a comparative example will be explained.

FIG. 1 is a cross-sectional view illustrating a variable resistance element 10 in accordance with a comparative example.

Referring to FIG. 1, the variable resistance element 10 includes a magnetic tunnel junction (MTJ) structure including a free layer 12 having a variable magnetization direction, a pinned layer 14 having a pinned magnetization direction and a tunnel barrier layer 13 interposed between the free layer 12 and the pinned layer 14.

The free layer 12 has a variable magnetization direction and also be referred to as a storage layer or the like.

The pinned layer 14 has a pinned magnetization direction and also be referred to as a reference layer or the like.

With the change of the magnetization direction of the free layer 13, the relative relationship of the magnetization directions of the free layer 13 and the pinned layer 15 also changes, which allows the variable resistance element 10 to store different data or represent different data bits. That is, the variable resistance element 10 functions as a memory cell.

The free layer 12 and the pinned layer 14 has a single-layer or multilayer structure including a ferromagnetic material. The magnetization direction of the free layer 12 is changed by spin transfer torque. The magnetization directions of the free layer 12 and the pinned layer 14 are substantially parallel to stacking directions of the free layer 13, the tunnel barrier layer 14 and the pinned layer 15. For example, the magnetization direction of the free layer 12 is changed between a downward direction and an upward direction, and the magnetization direction of the pinned layer 14 be fixed to a downward direction.

The tunnel barrier layer 13 includes an insulating oxide and allow the tunneling of electrons.

Further, the variable resistance element 10 may include various layers to improve characteristics of the MTJ structure. For example, the variable resistance element 10 may further includes an under layer 11 which is disposed below the MTJ structure and aids in improvement of characteristics of the MTJ. The under layer 11 may include a metal-containing layer.

Meanwhile, when the free layer 12 may have a single-layer structure, it should have a small thickness to have a perpendicular magnetization direction. This is because, in the single-magnetic layer, the magnetization direction becomes closer to horizontal as the thickness of the layer is increased.

However, when the thickness of the free layer 12 disposed over the under layer 11 is small, metals included in the under layer 11 may pass through the free layer 12 to diffuse into the tunnel barrier layer 13 or the pinned layer 14. The diffused metals may be trapped in the tunnel barrier layer 13 and/or the pinned layer 14 and function as a leakage path to cause problems in operation of the variable resistance element 10.

However, if the thickness of the free layer 12 is increased, it is difficult to keep the magnetization direction perpendicular. That is, the MTJ structure having vertical magnetization characteristics may not be implemented.

In order to overcome such problems, as shown in FIG. 1, the free layer 12 may be formed to have a three-layer structure. For example, the free layer 12 may include a first magnetic layer 12A, a spacer layer 12B and a second magnetic layer 12C.

In the free layer 12, spacer exchange coupling between the first magnetic layer 12A and the second magnetic layer 12C may be strengthened so that magnetization reversal may occur simultaneously in the first magnetic layer 12A and the second magnetic layer 12C. Therefore, an influence of a stray field generated when the free layer 12 is formed as a single-layer can be offset and perpendicular magnetic anisotropy of the free layer 12 can be increased.

However, when the free layer 12 is formed as a three-layer structure as above, there is a problem that a switching current Ic is increased as a volume of the free layer 12 is increased. In order to facilitate recording of information in the variable resistance element 10, it is necessary to lower the switching current Ic. Therefore, when the switching current Ic is increased, characteristics of the element cannot be stably maintained and problems can occur in operation of the variable resistance element 10.

A variable resistance element means an element capable of being switched between different resistance states in response to an applied bias (for example, a current or voltage). The variable resistance element may store different data according to the resistance state. That is, the variable resistance element may function as a memory cell. The memory cell may further include a selecting element coupled to the variable resistance element and controlling an access to the variable resistance element. Such memory cells may be arranged in various way to form a semiconductor memory.

In some implementations, the variable resistance element may include a magnetic tunnel junction (MTJ) structure which includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed therebetween. In response to a voltage or current of a sufficient amplitude applied to the variable resistance element, the magnetization direction of the free layer may be changed to a direction parallel or antiparallel to the magnetization direction of the pinned layer. Thus, the variable resistance element may switch between a low-resistance state and a high-resistance state to thereby store different data based on the different resistance states. The disclosed technology and its implementations can be used to provide an improved variable resistance element capable of satisfying or enhancing various characteristics required for the variable resistance element.

In implementations of the present disclosure, a free layer may be formed to have a three-layer structure satisfying specific conditions so that, in a variable resistance element, perpendicular magnetic anisotropy and tunnel magnetoresistance (TMR) can be increased and simultaneously a switching current Ic can be remarkably lowered.

FIG. 2 is a cross-sectional view illustrating a variable resistance element 100 in accordance with an implementation of the present disclosure.

Referring to FIG. 2, the variable resistance element 100 may include an MTJ structure including a free layer 130 having a variable magnetization direction, a pinned layer 150 having a pinned magnetization direction, and a tunnel barrier layer 140 interposed between the free layer 130 and the pinned layer 150.

The free layer 130 may have a variable magnetization direction that causes the MTJ structure to have a variable resistance value. With the change of the magnetization direction of the free layer 130, the relative relationship of the magnetization directions of the free layer 130 and the pinned layer 150 also changes, which allows the variable resistance element 100 to store different data or represent different data bits. The free layer 130 may also be referred as a storage layer or the like. The magnetization direction of the free layer 130 may be substantially perpendicular to a surface of the free layer 130, the tunnel barrier layer 140 and the pinned layer 150. In other words, the magnetization direction of the free layer 130 may be substantially parallel to the stacking direction of the free layer 130, the tunnel barrier layer 140 and the pinned layer 150. Therefore, the magnetization direction of the free layer 130 may be changed between a downward direction and an upward direction. The change in the magnetization direction of the free layer 130 may be induced by spin transfer torque.

The free layer 130 may include a first magnetic layer 132, a spacer 134 and a second magnetic layer 136. The first magnetic layer 132 is a layer far from the tunnel barrier layer 140, and the second magnetic layer 136 is a layer adjacent to the tunnel barrier layer 140.

Perpendicular magnetic anisotropy energy density (Ku1_(eff)) of the first magnetic layer 132 may be greater than perpendicular magnetic anisotropy energy density (Ku2_(eff)) of the second magnetic layer 136. That is, in the free layer 130 including the first magnetic layer 132, the spacer 134 and the second magnetic layer 136, condition of Ku1_(eff)>Ku2_(eff) may be satisfied.

If the condition of Ku1_(eff)>ku2_(eff) is satisfied, the second magnetic layer 136 which is adjacent to the tunnel barrier layer 130 may first undergo magnetization reversal in a smaller switching current Ic region. At this time, a stray field generated in the second magnetic layer 136 where magnetization reversal is made may facilitate magnetization reversal of the first magnetic layer 132, and subsequently the first magnetic layer 132 may undergo magnetization reversal in a smaller switching current Ic region.

Therefore, in comparison with the free layer 12 having a three-layer structure in accordance with the comparative example as shown in FIG. 1, the free layer 130 having a three-layer structure and satisfying the condition of Ku1_(eff)>Ku2_(eff) in accordance with the implementation can maintain high perpendicular magnetic anisotropy and remarkably reduce a switching current Ic.

Moreover, the free layer 130 may satisfy a condition that a spacer exchange coupling constant is equal to or less than 0.3. The condition of the spacer exchange coupling constant≤0.3 may be satisfied by an appropriate selection of the materials and the thickness of the spacer 134. When the spacer exchange coupling constant is equal to or less than 0.3, the first magnetic layer 132 and the second magnetic layer 136 may undergo magnetization reversals separately from each other, and the second magnetic layer 136 adjacent to the tunnel barrier layer 140 may first undergo magnetization reversal. Hence, a stray field generated by the second magnetic layer 136 may serve to assist magnetization reversal of the first magnetic layer 132. Then, the first magnetic layer 132 may undergo magnetization reversal in a small switching current Ic region. As a result, it is possible to lower the switching current Ic of the free layer 130 in the variable resistance element 100.

That is to say, in case of the free layer 12 in accordance with the comparative example shown in FIG. 1, the strong spacer exchange coupling between the first magnetic layer 12A and the second magnetic layer 12C causes simultaneous magnetization reversals of the first magnetic layer 12A and the second magnetic layer 12C to offset an influence of a stray field. However, in case of the free layer 130 in accordance with an implementation of the present disclosure the strength of the spacer exchange coupling may become generally weak, for example, the exchange coupling constant may be 0.3 or less to allow magnetization reversals of the first magnetic layer 132 and the second magnetic layer 136 separately from each other. In this way, a stray field generated by the second magnetic layer 136 which first undergoes the magnetization reversal may facilitate magnetization reversal of the first magnetic layer 132 to significantly lower the switching current Ic.

Each of the first magnetic layer 132 and the second magnetic layer 136 may be formed of or may include a ferromagnetic material. For example, each of the first magnetic layer 132 and the second magnetic layer 136 may be made or include an alloy based on Fe, Ni or Co such as a Co—Fe—B alloy, a Co—Fe—B—X ahoy (Wherein X may be Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, W or Pt), an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, a Co—Gd alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, a Co—Fe—Pd alloy, or the like, or may include a stack of metal layers, such as Co/Pt, Co/Pd, Co/Ir, Co/Ru, or the like, or may include alternate stack structures of magnetic materials and non-magnetic materials.

Each of the first and second magnetic layers 132 and 136 may be formed of a suitable material capable of satisfying the condition of Ku1_(eff)>Ku2_(eff).

The second magnetic layer 136 may have a single-layer or a multilayer structure including Co, Fe and B as a main component, which may be preferable in terms increasing tunnel magnetoresistance (TMR).

The first magnetic layer 132 may have a well-matched crystalline structure such as a hexagonal close packed (hcp) (0001) structure and a face centered cubic (fcc) (111) structure, or may have an amorphous structure. In an implementation, the first magnetic layer 132 may include a stack structure such as Co/Pt Co/Pd, Co/Ir, Co/Ru, or the like. In another implementation, the first magnetic layer 132 may include an alloy including Co as a main component such as an alloy including CoGd. In still another implementation, the first magnetic layer 132 may include a combination of the above mentioned materials.

In order to satisfy the condition ref Ku1_(eff)>Ku2_(eff), a thickness (t2) of the second magnetic layer 136 may be greater than a thickness (t1) of the first magnetic layer 132.

Further, the free layer 130 may further include a spacer 134 interposed between the first magnetic layer 132 and the second magnetic layer 136. The spacer 134 may serve to resolve a lattice structure difference and a lattice mismatch between the first magnetic layer 132 and the second magnetic layer 136.

A material and a thickness of the spacer 134 may be appropriately selected to satisfy the condition of the spacer exchange coupling constant≤0.3.

In an implementation, the spacer 134 may include an amorphous material,

In another implementation, the spacer 134 may include a metal, a metal nitride a metal oxide, or the like.

The tunnel barrier layer 140 may allow the tunneling of electrons in both data reading and data writing operations. In a write operation for storing new data, a high write current may be directed through the tunnel barrier layer 140 to change the magnetization direction of the free layer 130 and thus to change the resistance state of the MTJ for writing a new data bit. In a reading operation, a low reading current may be directed through the tunnel barrier layer 140 without changing the magnetization direction of the free layer 130 to measure the existing resistance state of the MTJ under the existing magnetization direction of the free layer 130 to read the stored data bit in the MTJ. The tunnel barrier layer 140 may be made or include a dielectric oxide, for example, an oxide such as MgO, CaO, SrO, TiO, VO, or NbO or the like.

The pinned layer 150 may have a pinned magnetization direction which contrasts with the magnetization direction of the free layer 130, and may be referred to as a reference layer or the like. In FIG. 2, the magnetization direction of the pinned layer 150 may be pinned in a downward direction. In some implementations, unlike that shown in FIG. 2, the magnetization direction of the pinned layer 150 may be pinned in an upward direction.

The pinned layer 150 may have a single-layer or multilayer structure including a ferromagnetic material. For example, the pinned layer 150 may be made or include an alloy based on Fe, Ni or Co, for example, an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy a Co—Pt alloy an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, or a Co—Fe—B alloy or the like, or may include a stack of metals, such as Co/Pt, or Co/Pd or the like.

If a voltage or current is applied to the variable resistance element 100, the magnetization direction of the free layer 130 may be changed by spin torque transfer. When the magnetization directions of the free layer 130 and the pinned layer 150 are parallel to each other, the variable resistance element 100 may be in a low resistance state to store a particularly designated digital data bit such as ‘0’, Conversely, when the magnetization directions of the free layer 130 and the pinned layer 150 are anti-parallel to each other, the variable resistance element 100 may be in a high resistance state to store a different designated digital data bit such as ‘1’. In some implementations, the variable resistance element 100 can be configured to store data bit ‘1’ when the magnetization directions of the free layer 130 and the pinned layer 150 are parallel to each other and to store data bit ‘0’ when the magnetization directions of the free layer 130 and the pinned layer 150 are anti-parallel to each other.

In some implementations, the variable resistance element 100 may further include one or more layers performing various functions to improve a characteristic of the MTJ structure. For example, the variable resistance element 100 may further include a buffer layer 110, an under layer 120, a spacer layer 160, a magnetic correction layer 170 and a capping layer 180.

The under layer 120 may be disposed below the free layer 130 to aid in improving perpendicular magnetic crystalline anisotropy of the free layer 130.

In the implementation the under layer 120 may be made or include a nitride or a carbide having a wurzite structure. For example, the under layer 120 may be made or include aluminum nitride (AlN).

In an implementation, the under layer 120 is formed of a nitride such as AlN and the free layer 130 is formed to satisfy the condition of Ku1_(eff)>Ku2_(eff) and the condition of the spacer exchange coupling constant≤0.3 so that perpendicular magnetic anisotropy of the free layer 130 can be maintained high, a driving current can be significantly lowered and thermal stability can be secured. As a result it is possible to improve performance of the variable resistance element 100.

The buffer layer 110 may be disposed under the under layer 120 and aid in crystal growth of the under layer 120. When the buffer layer 110 is formed under the under layer 120, it is possible to aid in crystal growth of the under layer 120 and thus improve perpendicular magnetic crystalline anisotropy of the free layer 130. The buffer layer 110 may have a single-layer or multilayer structure and may be made of a conductive material such as a metal, a metal alloy, a metal nitride, or a metal oxide, or a combination thereof. Moreover, the buffer layer 110 may be formed of a material having excellent compatibility with a lower electrode (not shown) in order to eliminate lattice constant mismatch between the lower electrode and the under layer 120. For example, the buffer layer 110 may be made of or include tantalum (Ta).

The magnetic correction layer 170 may serve to offset the effect of the stray magnetic field produced by the pinned layer 150. In this case, the effect of the stray magnetic field of the pinned layer 150 can decrease, and thus a biased magnetic field in the free layer 130 can decrease. The magnetic correction layer 170 may have a magnetization direction anti-parallel to the magnetization direction of the pinned layer 150. In an implementation when the pinned layer 150 has a downward magnetization direction, the magnetic correction layer 170 may have an upward magnetization direction. Conversely, when the pinned layer 150 has an upward magnetization direction, the magnetic correction layer 170 may have a downward magnetization direction. The magnetic correction layer 170 may have a single-layer or multilayer structure and may be made of a ferromagnetic material.

In this implementation, the magnetic correction layer 170 is located above the pinned layer 150, but the position thereof may be changed. For example, the magnetic correction layer 170 may also be located above, below, or next to the MTJ structure while it is patterned separately from the MTJ structure.

The spacer layer 160 may be interposed between the magnetic correction layer 170 and the pinned layer 150 and may function as a buffer therebetween. Further, the spacer layer 160 may serve to improve characteristics of the magnetic correction layer 170. The spacer layer 160 may be made of or include a noble metal such as ruthenium Ru).

The capping layer 180 may function as a hard mask for patterning the variable resistance element 100 and may be made of or include various conductive materials such as a metal. In some implementations the capping layer 180 may be made of a metallic material having almost none or a small number of pin holes and high resistance to wet and/or dry etching. For example, the capping layer 180 may be made of or include a noble metal such as ruthenium (Ru).

Although, in the above implementation, the free layer 130 is disposed below the pinned layer 150, in other implementations the free layer 130 may be disposed above the pinned layer 150.

The variable resistance element 100 as described above can have advantages as follows.

It is possible to keep perpendicular magnetic anisotropy of the free layer 130 high and remarkably lower the switching current Ic by forming the free layer 130 to include the first magnetic layer 132 and the second magnetic layer 136 which have different perpendicular magnetic anisotropy energy densities from each other and interposing the spacer 134 satisfying the condition of the spacer exchange coupling constant≤0.3 between the first magnetic layer 132 and the second magnetic layer 136.

That is, unlike the variable resistance element 10 in accordance with the comparative example of FIG. 1, in the variable resistance element 100 in accordance with the implementations, the first magnetic layer 132, the spacer 134 and the second magnetic layer 136 may be formed over the under layer 120 formed of a nitride, or the like so that the free layer 130 can satisfy the condition of Ku¹ _(eff)>Ku2_(eff) and the condition of the spacer exchange coupling constant≤0.3. Therefore, the second magnetic layer 136 adjacent to the tunnel barrier layer 140 may first undergo magnetization reversal in a smaller switching current c region and a stray field generated by the second magnetic layer 136 may facilitate magnetization reversal of the first magnetic layer 132. Then, the first magnetic layer 132 may undergo magnetization reversal in a smaller switching current Ic region.

Unlike the comparative example n which an influence of the stray field is offset, in an implementation of the present disclosure, the first magnetic layer 132 may undergo magnetization reversal by using the stray field generated by the second magnetic layer 136 which first undergoes magnetization reversal. Accordingly, the switching current. Ic can be significantly lowered, thermal stability can be secured and perpendicular magnetic anisotropy can be maintained high. As a result, it is possible to improve the characteristics of the variable resistance element 100.

A semiconductor memory device based on the variable resistance element 100 as disclosed in this document may include a cell array of such variable resistance elements 100 to store data. The semiconductor memory may further include various components such as lines, elements, etc. to drive or control each variable resistance element 100. This is exemplarily explained with reference to FIGS. 3 and 4.

FIG. 3 is a cross-sectional view illustrating memory device and a method for fabricating the same in accordance with an implementation of the present disclosure.

Referring to FIG. 3, the memory device, according to an implementation of the invention, may include a substrate 300, lower contacts 320 formed over the substrate 300, variable resistance elements 100 formed over the lower contacts 320 and upper contacts 350 formed over the variable resistance elements 100. For each variable resistance element 100, a specific structure as a switch or switching circuit/element, for example, a transistor, for controlling an access to a particular variable resistance element 100 can be provided over the substrate 300 to control the variable resistance element 100, where the switch can be turned on to select the variable resistance element 100 or turned off to de-select the variable resistance element 100. The lower contacts 320 may be disposed over the substrate 300, and couple a lower end of the variable resistance element 100 to a portion of the substrate 300 for example, a drain of the transistor as the switching circuit for the variable resistance element 100. The upper contact 350 may be disposed over the variable resistance element 100, and couple an upper end of the variable resistance element 100 to a certain line (not shown), for example, a bit line. In FIG. 3, two variable resistance elements 100 are shown as examples of the elements in an array of variable resistance elements 100.

The above memory device may be fabricated by the following processes.

First, the substrate 300 in which the transistor or the like is formed may be provided, and then, a first interlayer dielectric layer 310 may be formed over the substrate 300. Then the lower contact 320 may be formed by selectively etching the first interlayer dielectric layer 510 to form a hole H exposing a portion of the substrate 300 and filling the hole H with a conductive material. Then, the variable resistance element 100 may be formed by forming material layers for the variable resistance element 100 over the first interlayer dielectric layer 310 and the lower contact 320, and selectively etching the material layers. The etching process for forming the variable resistance element 100 may include the IBE method which has a strong physical etching characteristic. Then, a second interlayer dielectric layer 330 may be formed to cover the variable resistance element. Then, a third interlayer dielectric layer 340 may be formed over the variable resistance element 100 and the second interlayer dielectric layer 330, and then upper contacts 350 passing through the third interlayer dielectric layer 340 and coupled to an upper end of the variable resistance element 100 may be formed using similar processes as the ones used for forming the lower contacts 320 in the first dielectric layer 310.

In the memory device in accordance with this implementation, all layers forming the variable resistance element 100 may have sidewalls which are aligned with one another. That is because the variable resistance element 100 is formed through an etching process using one mask.

Unlike the implementation of FIG. 3, a part of the variable resistance element 100 may be patterned separately from other parts. This process is illustrated in FIG. 4.

FIG. 4 is a cross-sectional view illustrating a memory device and a method for fabricating the same in accordance with another implementation of the present disclosure. The following descriptions will be focused on the differences from the implementation of FIG. 3.

Referring to FIG. 4, the memory device in accordance with this implementation may include a variable resistance element 100 of which parts, for example, a buffer layer 110 and a under layer 120 have sidewalls that are not aligned with the other layers thereof. As shown in FIG. 4, the buffer layer 110 and the under layer 120 may have sidewalls which are aligned with lower contacts 420.

The memory device in FIG, 4 may be fabricated by tie following processes.

First, a first interlayer dielectric layer 410 may be formed over a substrate 400, and then selectively etched to form a hole H exposing a portion of the substrate 400. Then, the lower contacts 420 may be formed to fill a lower portion of the hole H. For example, the lower contacts 420 may be formed through a series of processes of forming a conductive material to cover the resultant structure having the hole formed therein, and removing a part of the conductive material through an etch back process or the like until the conductive material has a desired thickness. Then, the buffer layer 110 and an under layer 120 may be formed so as to fill the remaining portion the hole H. For example, the buffer layer 110 may be formed by forming a material layer for forming the buffer layer 110 which covers the resultant structure in which the lower contacts 420 is formed, and then removing a portion of the material layer by, for example, an etch-back process until the material layer has a desired thickness. Moreover, the under layer 120 may be formed by forming a material layer for forming the under layer 120 which covers the resultant structure in which the lower contacts 420 and the buffer layer 110 are formed, and then performing a planarization process such as a CMP (Chemical Mechanical Planarization) until a top surface of the first interlayer dielectric layer 410 is exposed. Then, the remaining parts of the variable resistance element 100 may be formed by forming material layers for forming the remaining layers of the variable resistance element 100 except the buffer layer 110 and the under layer 120 over the lower contacts 420 and the first interlayer dielectric layer 410. Subsequent processes are substantially the same as those as shown in FIG. 3.

In this implementation, the height which needs to be etched at a time in order to form the variable resistance element 100 can be reduced, which makes it possible to lower the difficulty level of the etching process.

Although in this implementation, the buffer layer 110 and the under layer 120 are buried in the hole H other parts of the variable resistance element 100 may also be buried as needed.

The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems. FIGS. 5 to 9 provide some examples of devices or systems that can implement the memory circuits disclosed herein.

FIG. 5 is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 5, a microprocessor 1000 may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor 1000 may include a memory unit 1010, an operation unit 1020, a control unit 1030, and so on. The microprocessor 1000 may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit 1010 may be a part which stores data in the microprocessor 1000, as a processor register, register or the like. The memory unit 1010 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 1010 may include various registers. The memory unit 1010 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 1020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit 1010 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit 1010 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the memory unit 1010 may be improved. As a consequence, operating characteristics of the microprocessor 1000 may be improved.

The operation unit 1020 may perform four arithmetical operations or logical operations according to results that the control unit 1030 decodes commands. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and so on.

The control unit 1030 may receive signals from the memory unit 1010, the operation unit 1020 and an external device of the microprocessor 1000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor 1000, and execute processing represented by programs.

The microprocessor 1000 according to this implementation may additionally include a cache memory unit 1040 which can temporarily store data to be inputted from an external device other than the memory unit 1010 or to be outputted to an external device. In this case, the cache memory unit 1040 may exchange data with the memory unit 1010, the operation unit 1020 and the control unit 1030 through a bus interface 1050.

FIG. 6 is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 6, a processor 1100 may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor 1100 may include a core unit 1110 which serves as the microprocessor, a cache memory unit 1120 which serves to storing data temporarily, and a bus interface 1130 for transferring data between internal and external devices. The processor 1100 may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit 1110 of this implementation may be a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit 1111, an operation unit 1112 and a control unit 1113.

The memory unit 1111 may be a part which stores data in the processor 1100, as a processor register, a register or the like. The memory unit 1111 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 1111 may include various registers. The memory unit 1111 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 1112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit 1112 may be a part which performs operations in the processor 1100. The operation unit 1112 may perform four arithmetical operations, logical operations, according to results that the control unit 1113 decodes commands, or the like. The operation unit 1112 may include at least one arithmetic logic unit (ALU) and so on. The control unit 1113 may receive signals from the memory unit 1111, the operation unit 1112 and an external device of the processor 1100, perform extraction, decoding of commands, controlling input and output of signals of processor 1100, and execute processing represented by programs.

The cache memory unit 1120 may be a part which temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at a high speed and an external device operating at a low speed. The cache memory unit 1120 may include a primary storage section 1121, a secondary storage section 1122 and a tertiary storage section 1123. In general, the cache memory unit 1120 includes the primary and secondary storage sections 1121 and 1122, and may include the tertiary storage section 1123 in the case where high storage capacity is required. As the occasion demands, the cache memory unit 1120 may include an increased number of storage sections. That is, the number of storage sections which are included in the cache memory unit 1120 may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections 1121, 1122 and 1123 store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections 1121, 1122 and 1123 are different, the speed of the primary storage section 1121 may be largest. At least one storage section of the primary storage section 1121, the secondary storage section 1122 and the tertiary storage section 1123 of the cache memory unit 1120 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit 1120 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the cache memory unit 1120 may be improved. As a consequence, operating characteristics of the processor 1100 may be improved.

Although it was shown in FIG. 6 that all the primary, secondary and tertiary storage sections 1121, 1122 and 1123 are configured inside the cache memory unit 1120, it is to be noted that all the primary, secondary and tertiary storage sections 1121, 1122 and 1123 of the cache memory unit 1120 may be configured outside the core unit 1110 and may compensate for a difference in data processing speed between the core unit 1110 and the external device. Meanwhile, it is to be noted that the primary storage section 1121 of the cache memory unit 1120 may be disposed inside the core unit 1110 and the secondary storage section 1122 and the tertiary storage section 1123 may be configured outside the core unit 1110 to strengthen the, function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections 1121, 1122 may be disposed inside the core units 1110 and tertiary storage sections 1123 may be disposed outside core units 1110.

The bus interface 1130 may be a part which connects the core unit 1110, the cache memory unit 1120 and external device and allows data to be efficiently transmitted.

The processor 1100 according to this implementation may include a plurality of core units 1110, and the plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or be connected through the bus interface 1130. The plurality of core units 1110 may be configured in the same way as the above-described configuration of the core unit 1110. In the case where the processor 1100 includes the plurality of core unit 1110, the primary storage section 1121 of the cache memory unit 1120 may be configured in each core unit 1110 in correspondence to the number of the plurality of core units 1110, and the secondary storage section 1122 and the tertiary storage section 1123 may be configured outside the plurality of core units 1110 in such a way as to be shared through the bus interface 1130. The processing speed of the primary storage section 1121 may be larger than the processing speeds of the secondary and tertiary storage section 1122 and 1123. In another implementation, the primary storage section 1121 and the secondary storage section 1122 may be configured in each core unit 1110 in correspondence to the number of the plurality of core units 1110, and the tertiary storage section 1123 may be configured outside the plurality of core units 1110 in such a way as to be shared through the bus interface 1130.

The processor 1100 according to this implementation may further include an embedded memory unit 1140 which stores data, a communication module unit 1150 which can transmit and receive data to and from an external device in wired or wireless manner, memory control unit 1160 which drives an external memory device, and a media processing unit 1170 which processes the data processed in the processor 1100 or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor 1100 may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units 1110 and the cache memory unit 1120 and with one another, through the bus interface 1130.

The embedded memory unit 1140 may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM) a memory with similar functions.

The communication module unit 1150 may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC) such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB) such as various devices which send and receive data without transmit lines, and so on.

The memory control unit 1160 is to administrate and process data transmitted between the processor 1100 and an external storage device operating according to a different communication standard. The memory control unit 1160 may include various memory controllers, for example, devices which may control Integrated Device Electronics (IDE), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), a solid state disk (SSD), External SATA (eSATA), Persona Computer Memory Card International Association (PCMCIA), a universal serial bus (USB), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit 1170 may process the data processed in the processor 1100 or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit 1170 may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 7 is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 7, a system 1200 as an apparatus for processing data may perform input, processing, output, communication storage, etc. to conduct a series of manipulations for data. The system 1200 may include a processor 1210, a main memory device 1220, an auxiliary memory device 1230, an interface device 1240, and so on. The system 1200 of this implementation may be various electronic systems which operate using processors, such as a computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor 1210 may decode inputted commands and processes operation, comparison, etc. for the data stored in the system 1200, and controls these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device 1220 is a storage which can temporarily store, call and execute program codes or data from the auxiliary memory device 1230 when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device 1220 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example the main memory device 1220 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the main memory device 1220 may be improved. As a consequence, operating characteristics of the system 1200 may be improved.

Also, the main memory device x 220 may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device 1220 may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM) and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device 1230 is a memory device for storing program codes or data. While the speed of the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The auxiliary memory device 1230 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device 1230 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the auxiliary memory device 1230 may be improved. As a consequence, operating characteristics of the system 1200 may be improved.

Also, the auxiliary memory device 1230 may further include a data storage system (see the reference numeral 1300 of FIG. 8) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), an universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device 1230 may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral 1300 of FIG. 9) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), an universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device 1240 may be to perform exchange of commands and data between the system 1200 of this implementation and an external device. The interface device 1240 may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (IMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 8 is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 8, a data storage system 1300 may include a storage device 1310 which has a nonvolatile characteristic as a component for storing data, a controller 1320 which controls the storage device 1310, an interface 1330 for connection with an external device, and a temporary storage device 1340 for storing data temporarily. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDRC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device 1310 may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM) and so on.

The controller 1320 may control exchange of data between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing an operation for, processing commands inputted through the interface 1330 from an outside of the data storage system 1300 and so on.

The interface 1330 is to perform exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 may be compatible with interfaces which are used in devices, such as an universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system 1300 is a disk type, the interface 1330 may be compatible with interfaces, such as Integrated Device Electronics (IDE), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI) External SATA (eSATA), Personal Computer Memory Card International Association (PCMCIA), an universal serial bus (USB), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface 1330 may be compatible with one or more interfaces having a different type from each other.

The temporary storage device 1340 can store data temporarily for efficiently transferring data between the interface 1330 and the storage device 1310 according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device 1340 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The temporary storage device 1340 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the storage device 1310 or the temporary storage device 1340 may be improved. As a consequence, operating characteristics and data storage characteristics of the data storage system 1300 may be improved.

FIG. 9 is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 9, a memory system 1400 may include a memory 1410 which has a nonvolatile characteristic as a component for storing data, a memory controller 1420 which controls the memory 1410, an interface 1430 for connection with an external device, and so on. The memory system 1400 may be a card type such as a solid state disk (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory 1410 for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory 1410 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the memory 1410 may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system 1400 may be improved.

Also, the memory 1410 according to this implementation may further include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller 1420 may control exchange of data between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing an operation for and processing commands inputted through the interface 1430 from an outside of the memory system 1400.

The interface 1430 is to perform exchange of commands and data between the memory system 1400 and the external device. The interface 1430 may be compatible with interfaces which are used in devices, such as an universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC) a compact flash (CF) card, and so on or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface 1430 may be compatible with one or more interfaces having a different type from each other.

The memory system 1400 according to this implementation may further include a buffer memory 1440 for efficiently transferring data between the interface 1430 and the memory 1410 according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory 1440 may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer. Through this, data storage characteristics of the buffer memory 1440 may be improved. As a consequence, operating characteristics and data storage characteristics of the memory system 1400 may be improved.

Moreover, the buffer memory 1440 according to this implementation may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory 1440 may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

Features in the above examples of electronic devices or systems in FIGS. 5 to 9 based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

Only a few implementations and examples are described. Other implementations enhancements and variations can be made based on what is described and illustrated in this patent document. 

What is claimed is:
 1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes: a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer includes: a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
 2. The electronic device of claim 1, wherein the free layer has a spacer exchange coupling constant equal to or less than 0.3.
 3. The electronic device of claim 1, wherein the second magnetic layer is disposed adjacent to the tunnel barrier layer and has a greater thickness than the first magnetic layer.
 4. The electronic device of claim 1, wherein the second magnetic layer includes an alloy including Co, Fe and B.
 5. The electronic device of claim 1, wherein the first magnetic layer has a crystalline structure including a hexagonal close packed (h p) (0001) structure or a face centered cubic (fcc) (111) structure, or an amorphous structure.
 6. The electronic device of claim 1, wherein the first magnetic layer includes a stack structure including Co/Pt Co/Pd, Co/Ir or Co/Ru, an alloy including Co, or a combination thereof.
 7. The electronic device of claim 1, wherein the spacer includes an amorphous material, a metal, a metal nitride, a metal oxide or a combination thereof, and wherein a material and a thickness of the spacer are selected so as to satisfy a condition of a spacer exchange coupling constant≤0.3.
 8. The electronic device of claim 1, wherein the semiconductor memory further includes an under layer disposed below the free layer and improving perpendicular magnetic anisotropy of the free layer.
 9. The electronic device of claim 8, wherein the under layer includes a nitride or a carbide having a wurzite structure.
 10. The electronic device of claim 8, wherein the under layer includes AIN.
 11. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes: a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first magnetic layer; a second magnetic layer; and a spacer interposed between the first magnetic Payer and the second magnetic layer, and wherein, at the time of magnetization reversal, the second magnetic layer first undergoes magnetization reversal and then the first magnetic layer undergoes magnetization reversal with the help of a stray field generated by the second magnetic layer.
 12. The electronic device of claim 11, wherein the free layer has a spacer exchange coupling constant equal to or less than 0.3.
 13. The electronic device of claim 11, wherein the second magnetic layer is disposed adjacent to the tunnel barrier layer and has a greater thickness than the first magnetic layer.
 14. The electronic device of claim 11, wherein the second magnetic layer includes an alloy including Co, Fe and B.
 15. The electronic device of claim 11, wherein the first magnetic layer has a crystalline structure including a hexagonal close packed (hcp) (0001) structure or a face centered cubic (fcc) (111) structure, or an amorphous structure.
 16. The electronic device of claim 11, wherein the first magnetic layer includes a stack structure including Co/Pt, Co/Pd, Co/Ir or Co/Ru, an alloy including Co, or a combination thereof.
 17. The electronic device of claim 11, wherein the spacer includes an amorphous material, a metal, a metal nitride, a metal oxide or a combination thereof, and wherein a material and a thickness of the spacer are selected so as to satisfy a condition of a spacer exchange coupling constant≤0.3.
 18. The electronic device of claim 11, wherein the semiconductor memory further includes an under layer disposed below the free layer and improving perpendicular magnetic anisotropy of the free layer.
 19. The electronic device of claim 18, wherein the under layer includes a nitride or a carbide having a wurzite structure.
 20. The electronic device of claim 18 wherein the under layer includes AlN. 